Ninety-five firms applied for access to the scheme's design automation tools. Twenty-four applied for financial support. The distance between the two numbers is preemptive non-application, not rejection. What in the Design-Linked Incentive Scheme's architecture holds this pattern, and what does it reveal about how India's incentive system processes capability that does not yet exist in revenue terms?
The DLI Scheme, announced in December 2021 under the ₹76,000 crore Semicon India Programme and implemented by C-DAC as the nodal agency, was designed with three components: infrastructure support (access to EDA tools and IP cores), a Product Design Linked Incentive (reimbursement of up to 50% of design expenditure, capped at ₹15 crore), and a Deployment Linked Incentive (6% to 4% of net sales turnover over five years, capped at ₹30 crore). The architecture appears comprehensive. The institutional reality is more specific.
The scheme applies the logic of a production-linked incentive to a pre-revenue startup. PLI rewards companies that have already achieved scale. DLI applies the same institutional architecture to companies that have not yet taped out their first chip. The verification frameworks, the milestone definitions, and the compliance expectations were inherited from a system designed for Samsung and Foxconn, not for a 15-person fabless startup burning through seed capital.
The Product Design Linked Incentive, at ₹15 crore, has been the primary disbursement channel. For a chip design that costs ₹30 to ₹50 crore to take from concept to tape-out, a 50% reimbursement capped at ₹15 crore covers less than half the journey. The shortfall is filled by the startup's own capital, angel investors, and whatever venture funding it can raise. This is where the scheme's most consequential restriction operates.
Approved applicants must maintain their domestic status for three years after claiming incentives. Domestic status means more than 50% of the capital must be beneficially owned by resident Indian citizens or Indian companies ultimately owned by resident Indian citizens. A fabless semiconductor startup that has designed a chip, completed the tape-out, validated the silicon, and is ready to scale needs venture capital. The most relevant VC capital for deep-tech semiconductor design comes from funds with global LP bases; precisely the funds whose ownership structures may dilute the Indian founders below the 51% threshold. The startup faces a binary choice: take the DLI incentive and restrict its cap table to domestic investors, or raise from the most capable global investors and forfeit the scheme entirely. Most promising startups choose the latter. This is why 24 companies have been approved against a target of 100. The scheme's ownership restriction is not a minor administrative condition. It is the single most consequential design choice in the entire programme, and it operates in direct tension with the government's stated objective of building a globally competitive fabless ecosystem.
The scale of this self-selection is visible in the application data itself. Of the 95 companies that have received access to electronic-design automation tools through the scheme's national EDA grid, only 24 have been approved for financial support under the product-development and deployment tracks. The distance between 95 firms accessing tool support and 24 firms applying for financial incentive is not rejection; it is preemptive non-application. Most eligible firms did not apply for the incentive component because the ownership clause made qualification structurally infeasible, and the founder pool that should most naturally anchor an Indian fabless ecosystem, Indian-origin engineers with two or three decades of foreign operating experience who have returned to India to set up a venture, is the pool the citizenship test disqualifies most cleanly. A founder who has spent two decades at a foreign chipmaker, returned to India to set up a fabless unit, and pays Indian taxes on that operating income cannot satisfy the eligibility test if the passport is not Indian. The beneficial-ownership test is citizenship-indexed, not residence-indexed, tax-indexed, or operating-record-indexed, and the DLI architecture does not recognise the other dimensions as substitutes. The scheme is not failing to attract the demographic it was designed to retain; it is structurally excluding that demographic by the definition of who counts as a domestic founder.
The nodal agency creates its own institutional friction. C-DAC, which processes applications, monitors milestones, and disburses incentives, is itself a chip design entity. It designs processors, develops IP cores, and participates in the same ecosystem it is tasked with nurturing. The conflict of interest is structural: the agency evaluating whether a startup's chip design merits support is also a potential competitor in the same design space. Karnataka's Semiconductor Fabless Accelerator Lab (SFAL), which operates without this conflict and has demonstrated effective startup engagement, has been proposed as an alternative implementing agency. The system has not acted on the proposal.
The ownership test is the first deterrent. The disclosure calculus is the second, and it operates on firms that can structurally satisfy the ownership clause. The DLI application requires the startup to submit detailed design approach, target architecture, go-to-market segments, and customer-engagement plans to the nodal agency as part of milestone verification. For a fabless venture, these are the core intellectual assets on which the company's valuation rests. A ₹15 crore incentive against the cost of sharing that information with an institutional counterparty that participates in the same design space is a calculation several applicants have resolved by not filing at all. Industry accounts further report that the nodal agency nudges applicants toward its own RISC-V-based processor ecosystem, on the reasoning that working within a single architecture simplifies scheme administration. Whether the nudge is an access pathway or an architectural constraint is not a question the scheme document answers; the applicant's choice of processor architecture becomes an informal qualifying dimension that the published eligibility matrix does not display.
The threshold requirement for the Deployment Linked Incentive compounds the problem. The startup must achieve a minimum net sales figure in a given year to qualify for the incentive in that year. If it falls short, no incentive is disbursed for that year, though the startup can claim in subsequent years if the threshold is met. For a company whose first commercial shipment may generate modest revenue as it builds its customer base, the threshold creates a distance between the moment the chip reaches the market and the moment the incentive begins to flow. The working capital required to bridge this distance is precisely the capital the ownership restriction makes difficult to raise.
The results reflect the architecture. Sixteen tape-outs. Six ASIC chips fabricated. Ten patents filed. Over 1,000 engineers trained. At the programme level, these are meaningful outputs. At the ecosystem level, they fall short of what the ₹76,000 crore programme was designed to yield. The total approved project outlay under the DLI scheme is approximately ₹803 crore, with disbursement tranched against milestones; the distance between allocation and realisation is the distance between the scheme's assumptions and the industry's reality.
The deeper institutional insight is this: India's incentive architecture knows how to reward production. It does not know how to incubate capability. PLI works because it incentivises companies that already have the capability to yield. DLI struggles because it applies the same incentive logic to companies that are building the capability for the first time. Production-linked incentives require scale. Design-linked incentives require patience, risk tolerance, and a willingness to fund setbacks. The committee architecture that processes DLI applications evaluates each proposal against milestones, thresholds, and compliance requirements designed for a manufacturing environment. A chip design startup that pivots its architecture mid-cycle, delays its tape-out to incorporate a new IP block, or loses a key engineer and needs six months to recover is not failing. It is doing what chip design startups do. The institutional framework treats these as deviations from the milestone plan. The venture capital ecosystem treats them as the normal course of business.
ISM 2.0, announced in Budget 2026-27 with a fiscal allocation of ₹1,000 crore for the year and complemented by the ₹8,000 crore outlay for the Modified Programme for Development of Semiconductor and Display Manufacturing Ecosystem, signals a recalibration of India's semiconductor ambition toward equipment, materials, full-stack domestic intellectual property, supply-chain resilience, and industry-led research and training. Within that recalibration, the anticipated second phase of the DLI scheme is reported to carry two structural shifts that speak directly to the current scheme's constraints. The first is a move from the reimbursement model, under which the startup spends its own capital first and claims up to half of it later, to a pari-passu funding structure in which the state co-invests alongside private capital rather than compensating cost after the fact. The second is a larger outlay, reportedly of the order of ₹5,000 crore, that would take the design-incentive ceiling closer to the capital requirement of a serious chip-design project. The first shift addresses the capital-availability-before-revenue constraint that currently forces the most promising startups to choose between the scheme and global venture capital; it is a structural improvement.
The same reporting flags a third proposed element that cuts the other way. The scheme is said to contemplate a clawback provision requiring founders to return three times the incentive received if the company is acquired by a foreign entity during a notified attribution window. Acquisition by a foreign major is not a design flaw in the fabless venture model; it is the exit mechanism around which semiconductor venture capital is structured globally, and a scheme that funds domestic design while penalising that exit has calibrated the incentive against the market reality the design capital is responding to. The institutional concern the clawback seeks to address, the loss of domestic IP to a foreign acquirer, is real. The instrument selected to address it, a triple-recovery penalty on the exit itself, transfers the institutional concern onto the founder as a personal liability at the precise moment the founder is monetising the risk capital the scheme was designed to complement. Whether the DLI scheme is ultimately restructured to address its ownership restriction, its threshold requirements, its nodal agency conflict, and the treatment of foreign acquisition in its clawback architecture will determine whether India's fabless ambition remains an experiment or becomes the foundation of a globally competitive design ecosystem.